1. Field
The present disclosure relates to methods and apparatus for closed loop control or supply and/or comparator common mode voltage of a successive approximation register (SAR). A method and apparatus for improving SAR analog to digital converter (ADC) performance by controlling the SAR supply and comparator common mode voltage is provided.
2. Background
Wireless communication devices have become smaller and more powerful, as well as more capable. Increasingly users rely on wireless communication devices for many of their day to day activities like checking email, accessing internet, as well as staying in touch. This has increased the burden on these devices and requires these devices to handle larger data, at higher speeds. In other words, increasing usage has increased the bandwidth requirement on wireless devices and also on the blocks used in wireless signal chain. A wireless receiver typically consists of low noise amplifier, a mixer, a baseband filter followed by an ADC (analog to digital converter). An analog to digital converter (ADC) is used to convert the incoming analog signals to a digital signal. Increasing the bandwidth, of a wireless system, requires ADC to operate at higher clock speeds. The methods and apparatus described herein enables an ADC to operate at higher clock speeds and thus improves the bandwidth of the wireless system. These techniques also apply to improving the performance of ADCs used in other applications.
Successive approximation ADC (SAR) topology is increasingly becoming the choice for ADCs used in many wireless systems. It has the advantage of scaling well with smaller geometry digital process and also consumes lower power than other ADC topologies. These features and advantages make it attractive for mobile wireless and other devices that must provide good performance with low power consumption. A SAR ADC that provides ‘N-bit’ output must to complete N-conversions, one after another, within one clock cycle. The time it takes the ADC to complete all N conversions is known as the conversion time and varies with process corner, temperature, and voltage. The voltages that control the speed of a SAR ADC are the supply voltage and the comparator common mode voltage. These voltages are designed for a nominal value, but they typically change above and below this value. In the slow corner of the operating envelope, such as occurs with extreme temperatures, if the supply voltage and/or the comparator common mode voltage is low, the SAR ADC will slow down and will not operate quickly enough to complete all conversions required by the clock speed of the operating system. This becomes a problem when trying to increase the clock frequency of a SAR ADC as high as possible. Merely programming these voltages higher does not solve the problem, as random variations, in addition to the increased voltage cause decreased reliability. In addition, setting the voltage higher increases the power consumption of the SAR ADC in other process corners where higher voltage is not needed. The ADC ends up using more power than needed.
To overcome this problem, SAR conversions could be stopped before completing all N conversions. However, this causes loss of accuracy. In other cases, the clock speed of SAR ADC can be reduced to accommodate the reduction in speed. This in turn will limit the signal bandwidth for which SAR ADC can be used.
There is a need in the art for methods and apparatus for improving SAR ADC performance by adaptively controlling voltages in SAR ADC, increasing only when it is slow and leaving it unchanged or reducing it when fast. In addition to improving performance in the slow corner, the methods and apparatus described herein also helps save power in typical and fast corners.